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Table 14.
Dynamic characteristics …continued
Symbol
Parameter
Conditions
Standard-mode
Fast-mode I 2 C-bus
Fast-mode Plus Unit
I 2 C-bus
I 2 C-bus
Min
Max
Min
Max
Min
Max
t PZH
OFF-state to HIGH propagation
OE to LEDn;
-
40
-
40
-
40
ns
delay
OUTNE[1:0] = 10 or 11
in MODE2 register
t PLH
LOW to HIGH propagation delay OE to LEDn;
-
40
-
40
-
40
ns
OUTNE[1:0] = 01
in MODE2 register
t PHL
HIGH to LOW propagation delay OE to LEDn;
-
60
-
60
-
60
ns
OUTNE[1:0] = 00
in MODE2 register
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms.
Disable bus time-out feature for DC operation.
t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V IL of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
The maximum t f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t f ) for the SDA output stage is specified at 250 ns. This allows series
protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f .
C b = total capacitance of one bus line in pF.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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